The present invention relates to a nonvolatile semiconductor memory device such as a flash memory. More particularly, the present invention relates to a multi-value nonvolatile semiconductor memory device which stores multi-value data in a memory cell.
Nonvolatile semiconductor memory devices, such as EPROM""s, EEPROM""s and flash memories, having a floating gate are widely used. Although description is given below using a flash memory as an example, the present invention can be applied to any nonvolatile semiconductor memory device, not limited to this, as long as it has a floating gate.
In a conventional semiconductor memory device, it is usual for each memory cell to store one of two values, that is, either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d, but in recent nonvolatile semiconductor memory devices, the trend is for each memory cell to store one of more than two values, for example, four values, that is, xe2x80x9c00xe2x80x9d, xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d, or xe2x80x9c11xe2x80x9d, so that the memory capacity can be increased without an increase in the number of memory cells. The present invention relates to such a multi-value nonvolatile semiconductor memory device that stores one of multiple values in each memory cell and that can be applied to any case where one of an arbitrary number of values is stored, but description is given below using a case where one of four values is stored as an example. In the description below, a multi-value nonvolatile semiconductor memory device is simply referred to as a multi-value memory.
A multi-value memory has a floating gate and the gate voltage (voltage of the control gate) at which a memory cell (transistor) is brought into the ON-state is changed by changing the quantity of charges (electrons) to be injected into the floating gate. A gate voltage at which a memory cell is brought into the ON-state is referred to as a threshold value here. In a multi-value memory, multiple boundary values are specified for a threshold value and a data value is assigned according to which area the threshold value belongs to, among the multiple areas specified by these boundary values. For example, in a case where the threshold value changes from 0V to 5V and four values are stored, first a boundary value of 2.5V, which is a half of 5V, is set so that the area is divided into two equal areas, and then two boundary values of 1.25V and 3.75V, which are the middle values in the divided two areas, respectively, are set so that each divided area is further divided into two areas, and thus the original area is divided into four equal areas. Then, for example, when the threshold value of a transistor is less than 1.25V, data xe2x80x9c00xe2x80x9d is assigned, and when between 1.25V and 2.5V, data xe2x80x9c01xe2x80x9d, when between 2.5V and 3.75V, data xe2x80x9c10xe2x80x9d, and when greater than 3.75V, data xe2x80x9c11xe2x80x9d is assigned. In this manner, each memory cell stores one of four values (that is, two bits). Generally, boundary values are set at equal intervals in a multi-value memory, as described above, because the algorithm of the write operation is simple.
FIG. 1 is a diagram that illustrates setting of boundary values and margins in a conventional multi-value memory. As described above, boundary values VT1, VT2 and VT3 are set at equal intervals and a data value is assigned to each of the four areas, respectively, which are divided by the boundary values VT1, VT2 and VT3.
Before data is written, an erase operation is performed that brings about a state in which the threshold value is V0 by removing charges once from the floating gate. V0 is a value far smaller than the lowest boundary value VT1 and is about 0V in the above-mentioned case. After the erase operation the write operation is performed, but when the write data is xe2x80x9c00xe2x80x9d, a write operation is not performed. This means that the threshold value of data xe2x80x9c00xe2x80x9d is V0, which corresponds to an erased state. When writing other data, the threshold value is detected after performing the write operation in which charges are injected into the floating gate little by little, and whether the lower limit threshold value of the write data is exceeded is checked. This action is repeated until the lower limit threshold value is exceeded, and when the lower limit threshold value is exceeded, charges are injected into the floating gate under a fixed condition so that the threshold value is increased by A. The threshold value A to be increased is determined so that the upper limit boundary value is not exceeded with variations in elements being taken into consideration. The threshold value A to be increased is the same regardless of the boundary values.
In the write operation described above, if the quantity of charges to be injected into the floating gate in one write operation is large, an error is produced, the maximum of which corresponds to the increment in the threshold value from the lower limit threshold value in one write operation, when it is detected that the threshold value is exceeded and, therefore, the smaller the quantity of charges to be injected into the floating gate in one write operation, the smaller the error. However, there occurs a problem that if the quantity of charges to be injected in one write operation is small, the number of times of repetition increases and the period of time required for the write operation is lengthened accordingly. Therefore, a method is adopted, in which as large a quantity of charge as possible but a quantity that ensures that the lower limit in the target range is not exceeded is injected the first time, then the above-mentioned operation is repeated while a small quantity of charges are injected each time.
Whether the threshold value exceeds the lower limit boundary value is detected by applying the voltage of the lower limit boundary value to the gate and judging whether the transistor is brought into the ON-state.
There are some cases where whether the threshold value exceeds the value that is the lower limit boundary value in the target range added by A is detected, instead of increasing the threshold value by A, by performing a fixed write operation after the threshold value exceeds the lower limit boundary value in the target range.
When the stored multi-value data is read, first, the boundary value VT2 is applied to the gate and whether the transistor is brought into the ON-state is detected. If it is brought into the ON-state, the boundary value VT1 is applied to the gate and whether the transistor is brought into the ON-state is detected, and if it is brought into the ON-state, the data is judged to be xe2x80x9c00xe2x80x9d, and if it is brought into the OFF-state, the data is judged to be xe2x80x9c01xe2x80x9d. If the application of VT2 brings the transistor into the OFF-state, then whether the application of the boundary value VT3 to the gate brings the transistor into the ON-state is detected, and if it is brought into the ON-state, the data is judged to be xe2x80x9c10xe2x80x9d and if it is brought into the OFF-state, the data is judged to be xe2x80x9c11xe2x80x9d. In this case, as the voltage of the boundary value is applied twice to the gate, the read time is lengthened. Therefore, there are some cases where the current when a fixed voltage is applied is detected as a threshold value and it is compared with the three boundary values in parallel. The present invention can be applied to any one of the cases.
The charges injected into the floating gate eventually leak, although gradually. When it is assumed that the leak current is i, the quantity of charges within the floating gate is Q, the capacitance of the floating gate is C, and the voltage of the floating gate is V, they are expressed by the following relationship
i=xe2x88x92dQ/dt=xe2x88x92Cxc3x97dV/dt
The voltage V of the floating gate is proportional to the threshold voltage. On the other hand, when the leak resistance is assumed to be R, then i=V/R, and when this is substituted into the above-mentioned expression, the following expression is obtained
V=xe2x88x92CRxc3x97dV/dt
Therefore, when the initial threshold value is assumed to be VS, the following expression is obtained
V=VSexp(xe2x88x92t/CR)
From this expression, it is found that the threshold value decreases while describing a curve of an exponential function, as shown in FIG. 2.
As shown in FIG. 1, in a conventional multi-value memory, the boundary values of the threshold value are spaced at identical intervals and at the same time, the threshold value A is the same, which is an increment from the lower limit boundary value in the write operation. The threshold value A that is an increment from the lower limit boundary value corresponds to a margin for leakage. The threshold value decreases as time elapses because of the leakage, and when it decreases below the lower limit of the range, that is, when it decreases by more than the margin, the range may be wrongly judged to be a different range.
FIG. 3 is a diagram that shows the relationship between the margin and the leakage. As shown in FIG. 3, when data xe2x80x9c01xe2x80x9d, xe2x80x9c10xe2x80x9d and xe2x80x9c11xe2x80x9d are written, charges are injected so that the threshold values are equal to the boundary values VT1, VT2 and VT3 added by the margin A, respectively. As described above, the threshold value decreases as time elapses describing a curve of an exponential function, therefore, the amount of decrease is larger for the data for which the quantity of injected charges is larger, and the period of time for the threshold value to decrease by the amount A is the shortest for the data xe2x80x9c11xe2x80x9d, that is, a period of time T3, a period of time T2 for the data xe2x80x9c10xe2x80x9d, is longer and a period of time T1 for the data xe2x80x9c01xe2x80x9d is the longest. In the case of xe2x80x9c00xe2x80x9d, a wrong judgment is unlikely to occur because there is no lower limit boundary value.
For a multi-value memory, a maintain period of the written data is defined and it is attempted to discover an element whose leak resistance is small in a test such as an accelerated test. However, it is difficult to discover an element, the maintain period of which is a year or longer, in the accelerated test and there occurs a problem that the ability to maintain data during the defined period is insufficient when it is put to practical use, even though it has passed the accelerated test.
The present invention has been developed to solve the above-mentioned problems and the object of the present invention is to realize a multi-value memory that has improved the data maintain period.
FIG. 4 is a diagram that illustrates the principle of the present invention.
In order to realize the above-mentioned object, the multi-value nonvolatile semiconductor memory device according to the present invention is characterized in that increments A1, A2 and A3 in the threshold, which correspond to the quantity of charges injected into the floating gate and which are added to the lower limit threshold values VT1, VT2 and VT3 of each range, respectively, in the data write operation, are set so as to be larger for the data corresponding to a state in which a larger quantity of charges are injected.
As described in FIG. 3, the larger the quantity of charge injected into the floating gate, the larger the amount of leakage and the larger the amount of decrease in the threshold value when the elapsed time is the same. Therefore, when the margin is the same, the period of time required for the threshold value to decrease by more than the margin is shorter for the data corresponding to a state in which a larger quantity of charges are injected. As the data maintain period of a semiconductor memory device is defined with the worst case being taken into consideration, even though the data maintain period of the data corresponding to a state in which a small quantity of charges are injected is long, the data maintain period in this case is defined by a value corresponding to a case where data, corresponding to a state in which a large quantity of charge are injected, is stored.
According to the present invention, the margins A1, A2 and A3 are set so as to be larger for the data corresponding to a state in which a larger quantity of charges are injected, as shown in FIG. 4. Therefore, the data maintain period in a case where data corresponding to a state in which a larger quantity of charges are injected is lengthened and the data maintain period of a semiconductor memory device can be lengthened. Ideally, if the periods of time required for the threshold values to decrease through leakage by the amounts corresponding to margins A1, A2 and A3, respectively, are set so as to be the same using the decay curves of the threshold value, the data maintain period of the semiconductor memory device can be lengthened further.
As described above, the margin is set so that the upper limit of each range is not exceeded, with the variations in elements or the like being taken into account. In order to extend a margin when writing data corresponding to a state in which a large quantity of charges are injected, it is necessary to extend the range corresponding to each data so that the larger the quantity of injected charges, the wider the range. Therefore, when each multi-value memory cell stores at least four values and there are at least three boundary values, the interval between boundary values is made wider for a range of threshold value of data corresponding to a state in which a larger quantity of charges are injected.
To make the margins different from each other, the write operation is performed under the same condition but the period of time for the write operation is selected in accordance with the write data, when charges are further injected into the floating gate in a state in which the threshold value indicates the lower limit of the range. In the case where the injection of charges into the floating gate is performed by the application of write pulse, the number of pulses is made to remain unchanged but the width of pulse is selected in accordance with the write data or the same pulse is used but the number of pulses is selected in accordance with the write data, when charges are further injected into the floating gate in a state in which the threshold value indicates the lower limit of the range.